Wafer scale fiber optic termination

ABSTRACT

An optical fiber terminator package ( 300 ) has a chip with a surface with one or more light emitting devices ( 314 ) and at least one photoreceptor ( 312 ) formed on or in the surface. A cap ( 302 ) is bonded to the surface of the chip to encapsulate the devices ( 312, 314 ). The cap ( 302 ) has one or more regions ( 316, 318 ) transparent to light passing to or from the devices ( 312, 314 ). The cap ( 302 ) has been bonded to the semiconductor chip at the wafer stage prior to separation of the wafer into individual packages.

TECHNICAL FIELD

This invention relates to the molding and application of protective capsto microelectronic semiconductor chips on a wafer scale as opposed toapplication on an individual chip basis. More particularly the inventionrelates to the molding and application of protective caps tosemiconductor chips incorporating light emitting devices or receivers orboth and the provision of integrated optical fiber connectors.

BACKGROUND ART

Semiconductor chips are normally packaged in a protective layer orlayers to protect the chip and its wire bonds from atmospheric andmechanical damage. Existing packaging systems typically use epoxymolding and thermal curing to create a solid protective layer around thechip. This is normally carried out on individually diced chips bonded tolead frames and so must be done many times for each wafer. Alternativemethods of packaging include hermetically sealed metal or ceramicpackages, and array packages such as ball grid array (BGA) and pin gridarray (PGA) packages. Recently wafer scale packaging (WSP) has startedto be used. This is carried out at the wafer stage before the chips areseparated. The use of molding and curing techniques subjects the waferto both mechanical and thermal stresses. In addition the protective capso formed is a solid piece of material and so cannot be used for MEMSdevices, since the MEMS device would be rendered inoperable by thepolymer material. Existing packaging systems for MEMS devices includethematically sealed packages for individual devices, or use silicon orglass wafer scale packaging, both of which are relatively high costoperation.

Devices which incorporate optically active devices, such as lightemitting devices or photoreceptors, also require a cap with at least aportion of the cap transparent to the relative light. The caps alsofrequently require a lens to focus light passing through the cap and sothe epoxy molding techniques cannot be used. The devices are typicallypackaged individually or use silicon or glass wafer scale packaging.

DISCLOSURE OF THE INVENTION

In one broad form the invention provides an optical fiber terminatorpackage including:

-   -   a) a semiconductor chip having a top surface and a bottom        surface and including at least one first optical device which        emits or receives electromagnetic radiation at one or more        wavelengths from the top surface;    -   b) a first hollow cap having a central portion and a first        perimeter wall extending from the perimeter edge of the central        portion with the free edge of the first perimeter wall bonded to        the top surface to provide a first cavity which, in plan view,        overlays at least part or all of at least one light emitting        device, said central portion including:        -   at least one region which is at least substantially            transparent or translucent to electromagnetic radiation at            said one or more wavelengths; and

wherein the first cap has been bonded to the semiconductor chip at thewafer stage prior to separation of the wafer into individual packages.

The package may include at least one region which refractselectromagnetic radiation passing therethrough.

The package may also include at least one first attachment means forattaching an electromagnetic radiation transmitting cable or fiber tothe cap, whereby at least some electromagnetic radiation transmittedbetween the at least one first optical device and the cable or fiberpasses through said at least one region.

The package may also include at least one second optical device whichemits or receives electromagnetic radiation at one or more wavelengthsfrom the top surface

The package may also include at least one second attachment means forattaching an electromagnetic radiation transmitting cable or fiber tothe cap, whereby at least some electromagnetic radiation transmittedbetween the at least one second optical device and the cable or fiberpasses through said at least one region.

The first optical device may be a light emitting device and the secondoptical device may be a photoreceptor.

The package may also include a second perimeter wall extending from theperiphery of the central portion away from the first perimeter wall.

The package may also include at least one recess in the central portion.

The package may also include a second cap bonded to the bottom surfaceof the chip.

The second cap bonded to the bottom surface of the chip may, in planview, overlay at least part or all of at least one first device and, ifpresent, the at least one second device.

The package may have a single light emitting device and a singlephotoreceptor. The two devices may act independently as a receiver and atransmitter for an optical network connection, for example.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a prior art method of forming protective caps onsemiconductor chips.

FIG. 2 shows a cross section of a prior art packaging made according tothe FIG. 1 method.

FIG. 3 shows a cross section of a prior art packaging of a MEMS device.

FIG. 4 shows a cross section through a MEMS device packaged according tothe invention.

FIG. 5 shows a possible device for forming molded caps;

FIG. 6 shows method of applying caps formed using the device of FIG. 5to a silicon wafer;

FIG. 7 shows the wafer and caps of FIG. 6 bonded together

FIG. 8 symbolically shows a method for applying molded caps to a siliconwafer according to the invention;

FIG. 9 shows the wafer and caps of FIG. 8 bonded together;

FIG. 10 shows an exploded cross sectional view of a device for formingthe protective caps.

FIG. 11 shows an exploded perspective view of the device of FIG. 10.

FIG. 12 shows a cross sectional view of the device of FIG. 10 at thecommencement of molding.

FIG. 13 shows the device of FIG. 10 after molding has finished and justbefore one side of the mold is released from the other side.

FIG. 13 a shows an expanded view of part of FIG. 13.

FIG. 14 shows a perspective view of the FIG. 10 device corresponding toFIG. 13.

FIG. 15 shows a cross sectional side view of the device after one of themolds has been partially removed.

FIG. 16 shows a cross sectional side view of the device after one of themolds has been fully removed.

FIG. 17 shows a cross sectional side view of the device undergoing anetch.

FIG. 18 shows a cross sectional side view of the device after undergoingan etch.

FIG. 19 shows a cross sectional side view of the device at thecommencement of application to a wafer and removal of the second mold.

FIG. 20 shows a cross sectional side view of a wafer after applicationof the caps.

FIG. 21 shows a cross sectional side view of a series of chips aftersingulation of the wafer.

FIG. 22 shows a cross sectional side view of a wafer with caps appliedto both sides, before singulation of the wafer.

FIG. 23 shows a cross sectional side view of a stage of manufacture of amolding wafer.

FIG. 24 shows a cross sectional side view of the wafer of FIG. 23 at anext stage of manufacture

FIG. 25 shows a cross sectional side view of the finished wafer offigure.

FIG. 26 shows a cross sectional view of a molding process using thewafer of FIG. 25.

FIG. 27 shows a cross sectional view of a semiconductor wafer havingoptical devices with packaging caps formed by the process of FIG. 26attached prior to separation of the wafer into separate packages.

FIG. 28 shows a cross sectional view of an optical semiconductor chip inits finished packaged form.

FIG. 29 shows a perspective view a first finished and packaged opticalfiber terminator device packaged according to the invention.

FIG. 30 shows a cross sectional side view the optical fiber terminatordevice of FIG. 29.

FIG. 31 shows a cross sectional side view of a molding device forforming the caps of the FIG. 29 package.

FIG. 32 shows an exploded perspective sectional view of the device ofFIG. 31 after forming of a cap.

FIG. 33 shows a perspective view of a part of the device of FIG. 31after forming of a cap.

FIG. 34 shows a cross sectional side view of a wafer having opticaldevices as the optical lens moldings are attached.

FIG. 35 shows a cross sectional side view of the wafer of figure afterremoval of the mold device

FIG. 36 shows a perspective sectional view of the wafer of FIG. 31 withattached optical lens moldings prior to singulation.

BEST MODE OF CARRYING OUT THE INVENTION

Referring to FIGS. 1 and 2 there is show a prior art method of formingprotective caps on semiconductor wafers on a wafer scale. Asemiconductor wafer 10 is clamped against a mold 12 having cavities 14formed therein and a liquid polymer material 16 is injected into thecavities 14. The polymer material sets to form solid protective caps 18.The wafer is then singulated using a wafer saw. This technique is notapplicable to wafers having MEMS devices formed thereon as the liquidpolymer material will surround the MEMS devices and stop them fromworking.

FIG. 3 shows the present prior art technique for protecting MEMSdevices. The MEMS chip 20 including the MEMS devices 24, shownsymbolically, is bonded to a silicon wafer 26. This may be carried outat the individual chip stage or at the wafer stage. The wafer 26 istypically etched using a crystallographic anisotropic etch using anetchant such as KOH to form a series of recesses 28 which correspond tothe locations of the MEMS devices. The wafers 26 are carefully alignedwith the MEMS wafer 20 and bonded thereto. While this can be aneffective means of packaging MEMS devices, it is expensive as itrequires an extra silicon (or sometimes glass) wafer, which must beetched to form the cavities.

FIG. 4 shows a MEMS wafer 30 having surface MEMS 32 formed thereon. Ahollow protective cap 34 of thermoplastic material made and bonded tothe wafer 30 according to the invention is provided so as to form amechanical and atmospheric protective barrier for the MEMS devices. Thecap 34 forms a cavity 36 with the wafer to allow the MEMS device(s) tooperate.

The use of molded thermoplastic hollow caps offers the possibility ofproviding inexpensive packaging. However, conventional techniques do notprovide the required accuracy and thermal stability required for microfabricated devices.

FIGS. 5 to 7 show a possible technique for packaging a semiconductorwafer 40 having a number of groups 42 of micro fabricated devices 44,shown symbolically, formed on or in an upper surface 46.

An array of caps 48 is formed using conventional injection moldingmethods and steel mold tools 50 & 52. The caps are supported on a sprule54 at the same nominal spacing as the groups 42. Using this method willalmost invariably lead to misalignment with resulting destruction ofMEMS devices, as shown in FIG. 7. In FIG. 7 the cap 48 a has beenaligned correctly with its group of MEMS devices 42 a. However thespacing between the caps is greater than the spacing of the groups sothat cap 48 b is not aligned correctly, but does not destroy any of theMEMS devices of its respective group 42 b. However, the caps 44 c & dare sufficiently misaligned that the perimeter walls of the caps overlayone or more of the MEMS devices 44, destroying their functionality.

This misalignment can be the result of a number of factors, includingdifferential thermal expansion of the sprule material compared to thesilicon wafer, non rigidity of the molded components and the lack ofmachinery designed for accurate alignment and bonding of polymers towafers using these techniques.

A solution is to use tools which have the same coefficient of thermalexpansion as the wafer, such as silicon and FIGS. 8 & 9 symbolicallyshow a technique using a silicon tool 60 to hold an array ofthermoplastics caps 62 as the caps are bonded to the silicon wafer 40.Since the tool 60 is formed of the same material as the wafer 40,changes in temperature will not result in changes in alignment; thespacing of the caps 60 will change by the same amount as the spacing ofthe groups 42 of MEMS devices 44. Thus, when bonded, all of the capswill be correctly aligned, as shown in FIG. 9. Additionally there ismuch experience in working silicon to the required accuracy.

FIGS. 10 to 16 schematically show a first system for creating andapplying hollow protective caps to wafers, preferably semiconductorwafers.

FIG. 10 shows a molding system 100 for forming the hollow protectivecaps shown in FIG. 4 which may be used with MEMS devices or any othermicro fabricated device. The molding system 100 includes two siliconwafers 102 & 104. The upper wafer 102 has been processed usingconventional lithography and deep silicon etching techniques to have aseries of recesses 106 in its lower surface 108. The lower wafer 104 hasbeen similarly processed so that its upper surface 110 has a series ofgrooves 112 which align with edges of the recesses 106. The recesses 106and grooves 112 are sized for the chip size of the wafer to be processedand repeat at centers corresponding to the repeat spacing on the wafer.In the embodiment shown the protective caps are designed for a MEMSinkjet printhead and so are very long relative to their width in planview. The recesses are rectangular, although the ends of the recessesare not shown. The ends of the grooves 112 are not shown but it is to beunderstood that the grooves 112 at each side of each recess are in factone groove which has a rectangular shape in plan view.

The grooves 112 for adjacent caps define a portion 114 of material whichhas not been etched. Similarly adjacent recesses 106 define a portion116 of material which has not been etched. These portions of material114 & 116 align with each other and when the two wafers are pressedtogether, the two wafers contact each other at these portions 114 & 116.

The two surfaces have been etched so that the groove 112 for theperimeter of the cap is all in the lower wafer 104 and the recess 104for the central portion is all in the upper wafer 102.

It is not essential that the mold wafers only contact on surfaces whichhave not been etched. Nor is it essential that the central portion isdefined by a recess in only one mold or that the perimeter walls bedefined by a groove or recess in only one mold. The effective split linebetween the molds may be located at any position desired and need not beplanar. However, planarity of the split line will typically simplifyfabrication of the molds.

The assembly 100 also includes an upper release or eject wafer 118 and alower release or eject wafer 120. These upper and lower release wafersare silicon wafers which have been processed utilizing conventionallithography and deep silicon etching techniques to have a series ofrelease pins 122 and 124 respectively. The upper and lower mold wafers102 & 104 are formed with corresponding holes 126 & 128 respectivelywhich receive the pins 122 & 124. The upper holes 126 are locatedgenerally toward the center or axis of each recess 106 whilst the lowerholes 128 are located in the grooves 112. However the location of theholes 126 and 128 is not especially critical and they may be placed asrequired for ejection of the molded caps.

The release pins 122 & 124 have a length greater than the depth of thecorresponding holes. When the free ends of the pins 122 align with theinner ends of the holes 126, there is a gap 130 between the upper moldwafer 102 and the upper release wafer 118. In this embodiment the lengthof the lower pins 124 is the same as the thickness of the lower moldwafer 104. However the length of the pins 124 may be greater than thethickness of the wafer or it may be less. When the length of the pins124 is less than the maximum thickness of the lower wafer 104 it needsto be greater than the depth of the holes 128, i.e. at least the reducedthickness of the wafer 104 at the grooves 112. The lower wafers 104 and120 are positioned with the pins 124 part way inserted in the holes 128but not extending beyond the holes 128 into the grooves 112 and with agap 132 between the two wafers. The pins 124 preferably extend to beflush with the ends of the holes so as to form a substantially planarbase to the groove 112.

The thickness of the mold and release wafers is about 800 microns whilstthe gaps 130 and 132 are of the order of 10 to 100 microns in thickness.However this is not critical.

The mold tools are preferably etched using cryogenic deep siliconetching rather than Bosch etching as to produce a smoother etch. Boschetching produces scalloping of etched side walls, such as the side wallsof the pin and cap recesses. The scalloping makes the release of themolds from the molded material more difficult. In comparison, using acryogenic etch results in much smother etched walls, with easier moldrelease.

A sheet 134 of thermoplastic material of about 200 to 500 microns inthickness is placed between the two wafers 102 & 104 and the assembly isplaced in a conventional wafer bonding machine, such as an EV 501,available from Electronic Visions Group of Sharding, Austria.

The assembly is mechanically pressed together in the machine but it willbe appreciated that the mold wafers may be urged toward each other todeform the thermoplastic sheet by applying an above ambient pressure tothe gaps 130 & 132. Alternatively other means may be used.

The sheet 134 may be heated by conduction but is preferably heated byradiation and preferably by using infrared radiation, as indicated byarrows 136 in FIG. 12. A combination of conductive and radiant heatingmay be used. The mold and release wafers 102 & 104 and 118 & 120respectively are formed of silicon, which is substantially transparentto infrared light of a wavelength in the range of about 1000 nm to about5000 nm. The material 134 chosen either intrinsically absorbs lightwithin this wavelength range or is doped so as to absorb light withinthis wavelength range. If the material 134 does not intrinsically absorbwithin this range, a suitable dopant is “carbon black” (amorphous carbonparticles) which absorbs light at these wavelengths. Other suitabledopants may be used.

The sheet 134 is placed between the two mold wafers and exposed toinfrared light at a suitable wavelength, as indicated by arrows 136. Theinfrared radiation is preferably supplied from both sides of the wafersand the sheet 134 to provide symmetrical heating, but this is notessential and the infrared radiation may be supplied from only one side.Because the silicon wafers are transparent to the infrared radiation,the infrared radiation passes through the wafers and is absorbed by thesheet 134. After heating to a suitable temperature the mold wafers maythen be urged together to deform the sheet 134. The wafers may bepressed together whilst the sheet 134 is being heated rather thanwaiting for the sheet 134 to be fully heated, particularly if conductiveheating is being used. If a material other then silicon is used heatingof the sheet 134 may be achieved using electromagnetic radiation atother wavelengths to which the material used is substantiallytransparent.

When processed in a wafer bonding machine the sheet 134 is molded to theshape of the cavity defined by the recess 106 and the groove 112. Thematerial is also substantially squeezed out of the gap between the twoportions 114 & 116, as indicated by arrows 142 in FIG. 13 a, to form aseries of caps 138

As previously mentioned, the molding wafers 102 & 102 are formed usingconventional lithography and deep silicon etching techniques. Theaccuracy of this process is dependant on the lithography and the resistused. The etch selectivity of silicon versus resist is typically betweenabout 40:1 and about 150:1, requiring a resist thickness for a 500 μmthick etch of between about 15 μm and 4 μm respectively. Using a contactor proximity mask, critical dimensions of around 2 μm can be achieved.Using steppers, electron beam or X-ray lithography the criticaldimensions can be reduced to less than a micron. Thus the material 134may be squeezed out totally from between the portions 114 & 116, totallyseparating the adjacent caps 136. Alternatively a thin layer 140 up toabout 2 microns thick may be left between the portions 114 & 116 betweenadjacent caps 136 due to the variation in position of the relativesurfaces due to manufacturing tolerances.

It is not essential that the mold wafers or the release wafers be madeof semiconductor materials or that they be processed using conventionallithography and deep silicon etching methods. Other materials andmethods may be used if desired. However, the use of similar materials tothe semiconductor wafers provides better accuracy since temperaturechanges have less effect. Also lithography and deep silicon etchingmethods are well understood and provide the degree of accuracy required.In addition, the one fabrication plant may be used for production ofboth the semiconductor devices and the molding apparatus.

It will be appreciated that the two mold wafers 102 & 104 will need tobe shaped so that there is space for the material to move into as it issqueezed out from between the two wafers.

After forming of the protective caps 138 it is preferred to remove thelower mold and release wafers 104 & 120 whilst leaving the material 134still attached to the upper mold wafer 102. A vacuum is applied to thegap 132 between the lower mold and release wafers. The release wafers118 & 120 are mounted in the assembly so as to be immovable whilst themold wafers 102 & 104 are movable perpendicular to the general plane ofthe wafers. Accordingly, the lower mold wafer 104 is drawn downwards tothe release wafer 120. The pins 124 of the release wafer 120 firmlypress against the material 134 and so retain the material 134 inposition and prevent it moving downwards with the lower mold wafer 124.The configuration of the assembly 100 after this stage is shown in FIG.15.

The lower release wafer 120 now only contacts the material 134 by pins124 and so it is now relatively easy to remove the lower release wafer120 from contact with the material 134 without dislodging the materialfrom the upper mold wafer 102. This is done and the assembly is then inthe configuration shown in FIG. 16, with the material 134 exposed forfurther processing and attachment to a wafer.

Whilst still attached to the upper mold, the sheet 134 is then subjectto an etch, preferably an oxygen plasma etch, from below, to remove thethin layer 140 of material, as shown in FIG. 17. The etch has littleeffect on the rest of the material due to the significant greater inthickness of the rest of the material. The etched assembly is shown inFIG. 18.

The assembly is then placed over a wafer 144 having a number of chipsformed on the wafer. Each chip has a plurality of MEMS devices 146. Thecomponents are aligned and then placed in a conventional wafer bondingmachine, such as an EV 501 to bond the caps 138 to the wafer. The arrayof chips is positioned so that each cap overlays part or all of a chip.The devices are shown symbolically and may be MEMS devices, MOEMSdevices, other micro fabricated devices, passive electronic elements orconventional semiconductor devices.

The assembly is removed from the wafer bonding machine and a vacuum isthen applied to the upper gap 130 so as to draw the upper mold wafer 102up toward the upper release wafer 118. Similar to the release of thelower mold wafer, the caps 138 are held in place by the pins 122 of theupper release wafer. Thus the chance of accidental detachment of any ofthe caps from the wafer due to the act of removing the upper mold waferis reduced, if not totally prevented.

The wafer 144 is now in a state where each chip is protected by adiscrete cap 138. The wafer can then be singulated into individual die.If the chips are arranged in a regular array, the conventional methodsof wafer singulation—sawing or scribing may be used. However, if theseparation lines between chips are not regular or if the chips are toofragile for sawing or scribing, deep reactive ion etching (DRIE) may beused to singulate the wafers. Although DRIE is much more expensive thanwafer sawing, this is moot if the wafer already required through waferdeep etching, as is the case with an increasing number of MEMS devices.If etching is used, the wafer 144 is next subject to a deep silicon etchin an etching system, such as an Alcatel 601 E or a Surface TechnologySystems Advanced Silicon Etch machine, to separate the wafer 144 intoindividual packages. This etch is carried out at a rate of about 2 to 5microns per minute and may be applied from either the cap side of thewafer or the bottom side of the wafer. The etch is highly anisotropic(directional) so there is relatively little etching of silicon sidewaysof the direction of the etch. If the etch is applied from the caps side,the caps 138 act as masks and only the silicon material between the capsis etched. The etching continues until all the silicon material betweenindividual chips is removed, thereby separating the chips 148 forsubsequent processing. If the etch is applied from below, a separatemask will need to be applied to the bottom surface of the wafer.

Any silicon exposed to the direction of the deep etch at the separationstage will be etched away. Thus if the etch is from the top (cap) sideany exposed silicon which needs to be retained, such as electrical bondpads, on the upper surface of the chip should be protected, such as by aresist, which must be removed prior to wire bonding. An alternative isto apply a mask to the lower surface of the wafer and to deep siliconetch from the rear. Alternatively second caps may be provided for thelower surface of the wafer, utilizing the same manufacturing methods asfor the upper caps and using the lower caps as masks for the etch. Byproviding both upper and lower caps at the wafer stage, each chip issubstantially completely packaged prior to singulation.

FIG. 22 shows a technique for providing protective caps for both theupper and lower surfaces. The figure shows a wafer 150 upon which havebeen formed a series of MEMS device chips 153 on an upper surface 154.Each chip 153 includes one or more MEMS devices 152 and optionally othermicro fabricated elements. A first set of protective caps 156 have beenformed on the upper surface 154 as per the techniques of the inventionpreviously described. The bond pads 158 of the individual chips 153 areon the upper surface 154 and are not covered by the protective caps 156.A second set of protective caps 160 have been formed on the lowersurface 162 of the wafer as per the techniques of the inventionpreviously described. The first and second sets of protective caps maybe applied to the wafer sequentially or may be applied to the wafersimultaneously. The order of application is not important. The secondset of caps 160 are located under each chip 153 but are larger than thefirst set 156 and extend under and beyond the bond pads 158.

The wafer 150 is then subject to a deep silicon etch from the lowersurface of the wafer as indicated by arrows 164, rather than from theupper surface, to separate the individual chips. The lower caps 160 thusact as a mask to the bond pads 158 and because the etching process isvery directional, only silicon between the lower caps 160 of theindividual chips is etched away. The bond pads 158 and other exposedparts on the upper surface within the outline of the lower caps aresubstantially unaffected by the etch and so the chips 152 will not bedamaged by the etch.

It will be appreciated that the provision of the second set of caps isonly a necessity where a hollow space is required; if a second set ofcaps is unnecessary or undesirable, a resist may be coated onto thelower surface with a grid pattern to leave areas between the chipsexposed for deep etching.

FIG. 28 shows a semiconductor laser chip package 250 incorporating a capaccording to the invention. The package includes a semiconductor chip252 on which have been formed a series of semiconductor laser devices254. For example these may be Vertical Cavity Surface Emitting Lasers(VCSELs). The VCSELs emit laser light generally perpendicular to theplane of the chip. The cap 256 has been formed and attached to the chipusing the inventive techniques described herein. However, the cap isformed of a material substantially transparent to the wavelength(s) ofthe light emitted by the VCSELs. In addition the cap has been formed soas to have a series of refractive lenses 258 in the cover portion 260.This is relatively easy to accomplish by fabricating the mould waferswith appropriately shaped recesses.

The steps involved in manufacture of the cap is shown in FIGS. 23 to 26.The cap is manufactured using the molding techniques previouslydescribed, but modified as below.

The lower mold wafer 200 used to form the cap needs to have a series oflens forming depressions formed in its molding surface. A resist mask201 is applied to the upper surface having a series of small holes 203in the mask 201 (see FIG. 23 a). The wafer is then subject to anisotropic etch. The size of the holes is relatively small and so theetching agent etches a hemispherical recess 202 behind each hole (seeFIG. 23 b). After etching the mask 201 is removed.

Referring to FIG. 23 c, the recesses 204 for the side walls of the capare formed by applying a second resist 206 to the upper surface 208having apertures 210 corresponding to the wall forming recesses. Ananisotropic deep silicon etch is applied to the upper surface to formthe wall forming recesses 204, as seen in FIG. 23. Referring to FIG. 24,a second resist 212 is applied to the lower surface with openings forforming ejector pin holes 214. An anisotropic deep silicon etch isapplied to the lower surface to form the ejector pin holes, as seen inFIG. 24. FIG. 25 shows a side view of the finished lower wafer.

A plastic sheet 222 is then molded using the molding techniquepreviously described, shown in FIG. 26. The upper cap 220 and upper andlower release wafers 224 & 226 respectively are as previously described.As with the standard technique, infrared radiation is used to heat theplastic sheet as pressure is applied, as indicated by arrows 228. Themolding forms caps 256 with a series of elongate lenses on the lowersurface of the caps. The caps are then bonded to a wafer as shown infigure using the methods previously described. The wafer is singulatedand necessary electrical connections made to produce the finishedpackage shown in FIG. 28.

A fiber optic terminator chip package is shown in FIG. 31. The packageincludes a semiconductor chip 300, a cap 302 which is both protectiveand optically active. The cap has two cylindrical recesses 304 & 306into which two optical fibers 308 & 310 respectively are affixed.

The chip has a photo sensor 312 for receiving light transmitted alongthe first optical fiber 308 and a laser 314 for emitting light fortransmission into the second optical fiber 310. The cap includes twolenses 316 & 318 for focusing light from the first optical fiber ontothe photo sensor and for collecting light from the laser and directingit into the second optical fiber. The chip package includes electricalbond pads 320 outside of the cap to which are affixed wires 322 forconnection to appropriate control and power circuitry.

FIG. 31 shows a molding device 350 for forming the caps. The lower mold352 is formed by etching through pin holes in a resist layer to formhemispherical recesses. The upper mold 354 is formed with twocylindrical posts 256, which will form the recesses 304 & 306 for theoptical fibers 308 & 310. The lower mold 352 has a lower perimeter wallforming recess 358 and the upper mold also has a upper perimeter wallforming recess 360. Whilst the drawings show the lower perimeter wallrecess 358 being narrower than the upper perimeter wall recess 360, thisis optional. The two wall recesses may have the same thickness or thelower wall may be thicker than the upper wall. Since in use the opticalfibers may apply a bending side loading to the cap, thicker upper wallsare preferred to prevent the fibers distorting the fiber receivingrecesses and becoming loose or pulling out. As seen in FIG. 32, theupper and lower molds each have four ejection pins 362 and 364respectively, located at the corners of the perimeter walls.

The molding assembly also includes a spacer wafer 366 which is locatedbetween the upper and lower mold wafers 352 & 354.

After forming an array of caps, the array is detached from the lowerwafer 352 as previously described and the array is attached to asemiconductor wafer 370 having multiple optical devices, as shown inFIG. 34. The caps are bonded to the wafer and the mold componentsremoved to leave the wafer with each set of optical devices protected bya cap, as seen in FIGS. 30 and 31.

The wafer 370 is singulated and electrical connections made to the bondpads of each chip. Optical fibers may then be inserted and bonded in thetwo recesses and the package is then in a usable state.

Whilst the package described has light emitting device(s) and lightreceiving device(s), it will be appreciated that the package may onlyhave light emitting device(s) or light receiving device(s). Thus apackage similar to that of FIG. 28 may be provided with an upper cap toallow for direct connection of one or more optical fibers. Where thedevice includes both light emitters and light receivers, the lightemitters and light receivers may be operated independently of eachother, such as in a connector for a optical network cable. Alternativelythe devices may be linked so that the package acts as a repeater.

Throughout the specification, reference is made to semiconductors andmore particularly silicon semiconductors. It is to be understood thatthe invention is not limited to use on semiconductors or silicon basedsemiconductors and has application to non semiconductor devices and tonon silicon based semiconductors, such as those based on galliumarsenide semiconductors.

Whilst the invention has been described with particular reference toMEMS devices, it is to be understood that the invention is not limitedto MEMS or MOEMS devices and has application to any devices which are ormay be bulk fabricated on a wafer.

It will be apparent to those skilled in the art that many obviousmodifications and variations may be made to the embodiments describedherein without departing from the spirit or scope of the invention.

1. An optical fiber terminator package including: a) a semiconductorchip having a top surface and a bottom surface and including a firstoptical device which can emit or receive electromagnetic radiation, thefirst optical device residing on or in the top surface; and b) a firsthollow cap including: (1) a central portion and first perimeter wallsextending from a perimeter edge of the central portion with free edgesof the first perimeter walls bonded to the top surface to provide afirst cavity; (2) the central portion overlying at least part or all ofthe first optical device: (3) a first region of the central portionwhich is substantially transparent or translucent to the electromagneticradiation; and (4) first attachment means for attaching a firstelectromagnetic radiation transmitting fiber to the first hollow cap; c)a second hollow cap bonded to the bottom surface of the semiconductorchip; wherein the first hollow cap has been bonded to the semiconductorchip at the wafer stage prior to separation of the wafer into individualpackages.
 2. The optical fiber terminator package of claim 1, whereinthe electromagnetic radiation transmitted between the first opticaldevice and the first fiber passes through the first region of thecentral portion.
 3. The optical fiber terminator package of claim 2,wherein the first region of the central portion is adapted to refractthe electromagnetic radiation passing therethrough.
 4. The optical fiberterminator package of claim 1, wherein the semiconductor chip furtherincludes a second optical device which can emit or receiveelectromagnetic radiation, the second optical device residing on or inthe top surface.
 5. The optical fiber terminator package of claim 4,wherein the first hollow cap further includes second attachment meansfor attaching a second electromagnetic radiation transmitting fiber tothe first hollow cap.
 6. The optical fiber terminator package of claim5, wherein the electromagnetic radiation transmitted between the secondoptical device and the second fiber passes through a second region ofthe central portion.
 7. The optical fiber terminator package of claim 6,wherein the second region of the central portion is adapted to refractthe electromagnetic radiation passing therethrough.
 8. The optical fiberterminator package of claim 4, wherein the semiconductor chip includesmore than two optical devices which can emit or receive electromagneticradiation, the more than two optical devices residing on or in the topsurface.
 9. The optical fiber terminator package of claim 8, wherein thefirst hollow cap further includes more than two attachment means forattaching more than two fibers to the first hollow cap.
 10. The opticalfiber terminator package of claim 1, wherein the first optical deviceemits or receives electromagnetic radiation at one or more wavelengths.11. The optical fiber terminator package of claim 1, the first hollowcap including second perimeter walls extending from the periphery of thecentral portion away from the first perimeter walls.
 12. The opticalfiber terminator package of claim 1, the first hollow cap including atleast one recess in the central portion.
 13. The optical fiberterminator package of claim 1, wherein the first optical device is alight emitting device or a photoreceptor.
 14. The optical fiberterminator package of claim 4, wherein the second optical device is alight emitting device or a photoreceptor.
 15. The optical fiberterminator package of claim 8, wherein the more than two optical devicesare individually either light emitting devices or a photoreceptors. 16.The optical fiber terminator package of claim 1, wherein the secondhollow cap, in plan view, overlaying at least part or all the firstoptical device.
 17. The optical fiber terminator package of claim 4,wherein the first optical device and the second optical device operateindependently.
 18. The optical fiber terminator package of claim 4,wherein the first optical device and the second optical device arelinked.